1. Field of the Invention
The invention relates to a semiconductor device and fabrication method thereof, and more particularly, to an approach of fabricating fin-shaped structure on NMOS region having top portion composed of silicon and bottom portion composed of silicon germanium and fin-shaped structure on PMOS region having top portion composed of silicon germanium and bottom portion composed of silicon.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
However, the overall architecture of fin-shaped structure still poses numerous problems in current FinFET fabrication, which not only affects the carrier mobility in the channel region but also influences overall performance of the device. Hence, how to improve the current FinFET process has become an important task in this field.